FPGA / VHDL / Hardware Systems
During graduate study and research at Washington University in St. Louis (2007–2012), I performed FPGA and VHDL development work spanning programmable networking systems, computer architecture, embedded digital systems, and hardware/software integration. Responsibilities included VHDL instruction as a Teaching Assistant in graduate computer architecture (CSE 560M) and computer systems design (CSE 462M); FPGA implementation projects on Xilinx Spartan platforms; programmable router architecture research in the Open Network Laboratory (ONL); and development of extensible packet-processing systems in the Applied Research Lab (ARL).
This page consolidates the supporting materials, projects, teaching artifacts, and publications from that period.
Technologies Used
VHDL · Xilinx ISE · Xilinx Spartan-3 FPGA · RTL design · FPGA synthesis, place-and-route, and timing analysis · digital logic design · computer architecture (MIPS, R10000, superscalar pipelines) · network processors (Intel IXP) · embedded systems · USB 2.0 (FTDI FT2232C) · VGA controller design · FIFO and dual-port memory design · hardware/software integration · packet-processing architectures.
Roles & Responsibilities
Graduate computer architecture. Led lectures on memory hierarchy and virtual memory; ran VHDL tutorials and architecture help sessions; graded student designs.
Graduate FPGA/VHDL systems design. Assisted lab sessions, ran design reviews, and coached student teams through Xilinx synthesis, timing, and board bring-up.
Built application frameworks for the Open Network Laboratory, a remotely accessible network-processor-based router platform. Co-authored the ONL paper at ANCS '08.
Developed plugin APIs and packet-processing extensions for ONL's programmable router. Designed core plugins for forwarding, counting, and filtering packets used in published P2P measurement and ISP-managed P2P experiments.
Graduate Coursework
Selected coursework at Washington University relevant to FPGA, VHDL, and computer architecture:
Graduate FPGA/VHDL systems design course. Semester project: the µAUS A-mode ultrasonic imaging subsystem implemented on a Xilinx Spartan-3 FPGA. See Projects.
Graduate computer architecture. Topics included superscalar pipelines, branch prediction, register renaming, and memory hierarchy. Final project: MIPS R10000 microarchitecture analysis. See Architecture.
Full graduate record covering M.S. and Ph.D. coursework.
VHDL / FPGA Teaching Materials
As Teaching Assistant for CSE 560M and CSE 462M, I prepared and delivered the materials below.
Instructional deck used in weekly VHDL help sessions for graduate CSE 462M students. Covers VHDL syntax, RTL coding style, simulation, and common synthesis pitfalls. Author and presenter.
Guest lecture covering memory hierarchy and virtual memory. Delivered as part of the graduate architecture TA rotation.
TA calendar documenting VHDL tutorials, help sessions, and lectures delivered to satisfy the CSE department's 14-hour teaching requirement.
FPGA / Embedded Systems Projects
CSE 462M semester project. Designed and implemented an A-mode diagnostic ultrasound subsystem on a Xilinx XC3S200 Spartan-3 FPGA with an FTDI FT2232C USB 2.0 bridge. Subsystem partitioned into four VHDL components — envelope detector, data controller, VGA controller, and system controller — with FIFO and dual-port-memory paths to a live 1024×768 VGA display and a host PC. Demonstrates RTL implementation, FPGA synthesis and timing closure, custom adapter-board design, and hardware/software integration across the FPGA, USB bridge, and a custom Microsoft C++ PC application. Co-author and implementer.
Designed and implemented Luigi32, a 32-bit pipelined RISC processor, in VHDL: instruction set, datapath, control logic, and a five-stage pipeline (fetch, decode, execute, memory, writeback). Linked deck is the project presentation. Co-designer and implementer.
Computer Architecture Coursework
CSE 560M final exam paper analyzing the MIPS R10000 superscalar dynamically-scheduled processor: instruction fetch and branch prediction, decode and register renaming, dispatch queues, execution pipelines, and the L1/L2 memory hierarchy. Author.
Graduate systems-design presentation slides covering datapath, control, and FPGA implementation tradeoffs.
ONL / ARL Research Materials
Architecture overview of ONL, the remotely accessible network-processor-based router platform used for the published ANCS '08 paper and downstream P2P measurement work. Co-author of plugin APIs for forwarding, counting, and packet filtering.
Selected Publications
Peer-reviewed publications that depend on the FPGA, programmable-router, and packet-processing work above.
References & Supporting Artifacts
All artifacts above, grouped for quick review. Roles are noted on each entry.